In the context of digital signaling, “synchronization” is the process of latching a signal between first and second non-aligned clock domains. Absent proper controls, the result of this latching can be somewhat unpredictable. There are three scenarios: a signal to be latched can be caught, a signal to be latched can be caught on the next clock edge, or a signal to be latched can be partly caught. The last scenario is the worst, as a “meta-stable” value (i.e., a value that is neither a “1” nor a “0”) can be latched. A latch that is in a meta-stable state can persist in this state for a long period of time, especially if the latch has low gain (or feedback). The latch can then propagate its meta-stable value to other circuits, which can cause illegal states and other problems.
To prevent the latching of a meta-stable state, a special latch with high gain is typically used. This latch is called a “resolving latch”. In addition, the latch is given enough time to resolve, such that any meta-stable value has been forced to a “0” or a “1” before it is sent to other circuits. However, even with these techniques, meta-stable events will theoretically occur if given enough time (perhaps 10,000 years).
Synchronization is accomplished by a “synchronizer”. Traditionally, a synchronizer waits for incoming data to arrive, and then synchronizes the data into the new clock domain. The resolve time of the synchronizer is typically a multiple or fraction of cycles of the new clock domain (e.g., ½, 1, 1½, 2 . . . ). This granularity can often force difficult decisions and/or design requirements. For example, designing a more aggressive resolving latch may be able to regain ½ cycles of latency, but at an increased cost and using more chip area.